A three day extensive workshop on VLSI Mask Design was conducted at the West Bengal University of Technology (WBUT), Kolkata, from October 12th to October 14th, 2009.

Conducted in collaboration with West Bengal University of Technology and Cadence, Intel’s partners of the EDA (Electronic Design Automation) industry, the workshop was held to benefit participants to systematically integrate VLSI Mask Design curriculum in their respective institutions. Twenty engineering faculties from reputed technology institutions participated in the workshop to discuss the industry relevance of a specialized curriculum like Mask Design.

Ms. Valsa Williams, Head Corporate Affairs (North & East), commenced the workshop with an overview of Intel Higher Education Program. She reminded the participants that they played a catalytic role in the implementation and integration of VLSI Mask design curriculum in their institutions.

“It has enthused some of the faculties of the affiliated colleges, who have attended the workshop with great expectations, to join in this program with the University.”
- Prof. Amitabha Sinha, Director, School of Information Technology, West Bengal University of Technology

Mr. Krishnaraj Vanavadiya and Mr. Umapathy J., from Intel India spoke to the participant audience on Industry Relevance of Mask Design Curriculum and Technical Challenges with sub-45nm VLSI Layout respectively.

An Interactive session was also organized where Intel technologists interacted with B. Tech and M. tech Students and discussed the industry academia relationship and the opportunities after higher education. The session was very well appreciated by the students.

As Prof. Harpal Thethi, Kalinga Institute of Industrial Technology rightly stated “The presentations were good, touched all the important aspects of Mask Design. The first day started with a great presentation by Mr. Krishnaraj (Intel) and the best was the hands-on session on Cadence tools.”