Intel Fellow and Director, System-on-Chip Architecture
Intel Corporation
Dr. Raj Yavatkar is an Intel Fellow and Director of the System-on-Chip (SoC) Architecture. He leads the development of modular design and validation technologies to enable high-integration SoC products with a quick turn-around time.
Dr. Yavatkar has held several positions at Intel including leading platform validation architecture for Intel's CPU and chipset products. He led the formation of the Systems Technology Lab involved in advanced R&D in the areas of system architecture and platform technologies. From 1999 through 2004, he was the Chief Software Architect for Intel's IXP family of network processors.
At Intel, Dr. Yavatkar also led Intel's advanced research and development activities in internet quality of service and programmable networks. He designed a framework for policy-based network management that led to development of Internet standards.
Dr. Yavatkar is an IEEE Fellow and is recognized as a leading expert in the networking industry. He received his Ph.D. in Computer Science from Purdue University in 1989 and holds fourteen patents, with more than 20 pending. He was the General Chair of ACM Sigcomm 2004 and ACM/IEEE ANCS 2007. Raj has authored or co-authored five Internet standards. Dr. Yavatkar has also published more than 40 papers in academic journals and conferences and has co-authored the book, Inside the Internet's Resource Reservation Protocol (RSVP) published by John Wiley.
Raj serves on the editorial board of the IEEE Network magazine and previously served as an editor of Computer Communications, ACM/Springer-Verlag Journal on Multimedia Systems and Kluwer Multimedia Tools and Applications. He also served as Vice-Chairman of the Network Processing Forum, which developed standards for the network processing industry.
Before he joined Intel, Raj was a tenured Associate Professor at the University of Kentucky and a Visiting Research Professor at the International Computer Science Institute and the University of California-Berkeley.
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Presentation Title
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SoC Research – where are we headed?
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Abstract:
Given the thriving SoC (System-on-Chip) ecosystem and Intel’s push for x86-based SoCs to serve a wide variety of market segments, the SoC design/development is now an important area of research. Smaller and smaller geometries, and higher and higher levels of on-die integration pose an interesting set of challenges that must be solved to meet a wide range of requirements. This talk will describe the target usage areas of IA-based SoCs, summarize a set of research challenges, and suggest a few directions.
Intel Fellow and Director of Circuit Technology Research
Intel Corporation
Vivek De is an Intel Fellow and Director of Circuit Technology Research in the Corporate Technology Group. In his current role, he provides strategic direction for future circuit technologies and is responsible for aligning Intel’s circuit research with technology scaling challenges. He has published 167 technical papers in refereed international conferences and journals in the areas of low power and high performance circuit technology. He holds 146 patents with 48 more patents filed (pending). He received an Intel Achievement Award for his contributions to a novel integrated voltage regulator technology. He has chaired and served in technical program committees of several prominent international conferences. He is currently an Associate Editor of the IEEE Transactions on Circuits and Systems. He received his Bachelor’s degree in Electrical Engineering from the Indian Institute of Technology in Madras, India in 1985 and his Master’s degree in Electrical Engineering from Duke University in 1986. He received a Ph.D. in Electrical Engineering from Rensselaer Polytechnic Institute in 1992.
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Presentation Title
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Design Challenges and Opportunities for Future Processor Platforms with Wide Dynamic Range
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Abstract:
Future processor platforms must provide ever wider dynamic range of performance and power to simultaneously meet the demands of hardware responsiveness, burst-mode performance and sustained throughput computing with maximum energy efficiency. Multi-core and System-On-Chip (SoC) processor and platform designs of the future must achieve wider range of voltage and frequency as well as optimal dynamic allocation of power budgets to different components in order to provide the best user experience under stringent thermal and energy consumption constraints. A minimal set of designs must also support a large number of platform segments spanning enterprise servers at the high end to Mobile-Internet-Devices (MID) at the low end to improve cost and Time-To-Market (TTM). We will discuss several design and technology limits to achieving wider voltage-frequency range in processors. We will present some reconfiguration, resiliency and adaptation techniques as well as research opportunities in these areas to overcome these barriers and enable more efficient dynamic power reallocations among platform components.
Intel Fellow, Software and Solutions Group
Intel Corporation
Geoff Lowney is an Intel Fellow in the Software and Solutions Group. He serves as a technical leader and manager of an advanced development group investigating new software technology for Intel’s future processors. Lowney has a broad background in compiler technology, computer architecture and software tools. He has researched and developed systems for binary optimization and instrumentation, parallel programming, speculative execution, predication, profile-directed compilation, instruction scheduling, and prefetching. Lowney represented Intel in China as the Intel “Fellow-in-Residence” in 2006 and 2007. Before working at Intel, he worked to develop the Alpha microprocessor at Digitial Equipment, and he was a principal in developing the Multiflow compiler, which has served as the basis for many modern industrial compilers. He has a BA in mathematics and PhD in computer science from Yale.
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Presentation Title
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Parallel Programming for Multi-core Processors
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Abstract:
Future processors will have more parallelism. They will have multiple cores, and each core will support multi-threading and SIMD vector instructions. To support multi-core processors effectively, programs will need to express parallelism. New programming models are being created to enable writing parallel programs. At Intel, we are developing compilers and tools to support the development of parallel programs that scale across a wide range of multi-core processors. In this talk, I will discuss the work we are doing to support parallel programming for multi-core. I will also present some research we are doing with academic partners on parallel programming.
General Manager
Intel Asia-Pacific Research & Development Co., Ltd
Wen-Hann Wang is vice president of the Software and Solutions Group, General Manager of Intel Asia-Pacific Research & Development Ltd, and general manager of the Software and Solutions and Product Development in China. Prior to his current assignment, he served as general manager of the Middleware Products Division in the Intel Software and Solution Group.
Wang joined Intel in 1991 as a PentiumPro Platform architect, working on the highly successful P6 product family. His platform architecture and analysis work was instrumental in the creation of the Xeon server product line. He served as platform infrastructure research manager of the newly formed Intel Microprocessor Research Lab (MRL) in 1995 and later became director of the Emerging Platforms Lab, delivering cutting-edge technologies and reference platforms for Intel product groups.
In 2000, Wang relocated to Shanghai to head up the Technology Development Division of SSG, developing software technologies and reference designs to accelerate growth in emerging markets.
Wang holds 15 patents and has received numerous technical awards, including the Influential Paper Award at ACM/IEEE International Symposium on Computer Architectures. Prior to joining Intel, he was a research staff member at the IBM T. J. Watson Research Center.
Wang received a bachelor's degree in electrical engineering from National Taiwan University in 1981, a master in electronic engineering from Philips International Institute of Technological Studies (Eindhoven, Netherlands) in 1985, and a Ph.D. in computer science from the University of Washington in 1989.
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Presentation Title
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Establishing a foundation for IT industry innovation – Intel Software makes the difference
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Abstract:
While it may be less visible than its hardware counterpart, Intel Software has been powering many exciting innovations in the IT world. It is software that helps bring the Intel® processors to life. It is software that enables us humans to interact with the hardware. It is software that unlocks the full potential of hardware. And when it comes to making Intel CPUs really perform, it is Intel Software that makes the difference.
In this keynote I will give an overview of the basic components of Intel’s software business. I will then describe key innovations that Intel Software has brought to the community. I will close with a number of exciting initiatives and projects that Intel Software is pursuing and invite Asia academic community to get connected to pursue an exciting new chapter of computing.
Vice President, Corporate Technology Group,
Director, Intel Research
Intel Corporation
Andrew Chien is vice president of the Corporate Technology Group and director of Research for Intel Corporation. Chien previously served as the Science Applications International Corporation Endowed Chair Professor in the department of computer science and engineering, and the founding director of the Center for Networked Systems at the University of California at San Diego. CNS is a university-industry alliance focused on developing technologies for robust, secure, and open networked systems.
For more than 20 years, Chien has been a global leader in research and the development of high-performance computing systems. His expertise includes networking, Grids, high performance clusters, distributed systems, computer architecture, high speed routing networks, compilers, and object oriented programming languages. He is a Fellow of the American Association for Advancement of Science (AAAS), a Fellow of the Association for Computing Machinery (ACM) and a Fellow of Institute of Electrical and Electronics Engineers (IEEE), and has published over 130 technical papers.
From 1990 to 1998, Chien was a professor at the University of Illinois at Urbana-Champaign. During that time, he held joint appointments with both the National Center for Supercomputing Applications (NCSA) and the National Partnership for Advanced Computational Infrastructure (NPACI), working on large-scale clusters. In 1999 he co-founded Entropia, Inc., an enterprise desktop Grid company. Chien received his bachelor's in electrical engineering, master's in computer science, and Ph.D. in computer science from the Massachusetts Institute of Technology.
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Presentation Title
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Enriching work and daily life with “Essential Computing” in Intel Research
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Abstract:
Over the past four decades, computing has excelled at analytical and clerical tasks, but in the 21st century, the center of gravity has shifted -- mobile computing devices are transforming society, empowering a broad range of social and personal activities. Intel Research’s bold “Essential Computing” vision is focused on creating research breakthroughs which make technology more intuitive, helpful and robust. Such capabilities allow computing to enhance the essence of our lives – not just our work, but our personal relationships and growth, sense of community, and life experience.
Central to this vision is a major research effort to enable “Everyday Sensing and Perception” which involves sensors, vision, machine learning and human interaction to achieve an unprecedented new capability. Under the Essential Computing vision, our research activities are organized into six multidisciplinary themes: “Personal Awareness”, increasing the ability of computing systems to conform to and support our personal needs, habits, and ambitions, “Richly Communicative”, which allows us to easily form and enrich relationships, “Physicality”, which actuates everyday objects, connecting the cyber and physical worlds, “Concealing Complexity”, to simplify every aspect of use and configuration of technology -- it just works!, “Data Rich”, unleashing the power of Internet-scale data sets, and “Biosensors”, connecting the biological and computing worlds at a molecular level.
Director Software Products and Multi-core Evangelist
Intel Corporation
James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief evangelist as well as their director of sales and marketing. Reinders is the author of a recent Nutshell book "Intel Threading Building Blocks" from O'Reilly Media which has been translated this year to Japanese and Chinese. James is a columnist for the "The Gauntlet" found online at
http://go-parallel.com
, and author of the book "VTune Performance Analyzer Essentials" from Intel Press and has published numerous articles and is widely interviewed on parallelism. James received his B.S.E. in Electrical and Computing Engineering and M.S.E. in Computer Engineering from the University of Michigan.
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Presentation Title
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Thinking Parallel
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Abstract:
Many software developers are indeed moving to use parallelism and few know more about what is actually happening than James Reinders. James will share Intel’s most recent and extensive experiences with software developers working on parallelism, and talk about what is working and what is not working. While adding parallelism is not an easy task, you may be surprised how fast it is being added by software developers. James will also explore the changing scene of parallel programming tools and languages being used by professionals, and make some predictions about the future as well explain what Intel will do in 2009 to help continue the march toward more and more parallelism in processors and in software. James will be giving this talk just a week before Microsoft’s PDC conference which is held only every two or three years. James has promised to share as much as he is allowed to share about what Intel and Microsoft will be saying and announcing about parallelism a week later.
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