Intel Software College course architect
Intel Corporation
Michael Wrinn is a senior course architect in the Intel Software College, where he collaborates with universities to bring parallel computing to the mainstream of undergraduate education. Prior assignments include managing Intel's software engineering lab in Shanghai, and directing the human interface technology research. He was Intel's representative to the committee which produced the first OpenMP specification, and remains active in the parallel computing community. Before joining Intel, Michael worked at Accelrys (San Diego), implementing commercial and research simulation codes on a wide variety of parallel/HPC systems. He holds a Ph.D. (in quantum mechanics) and a B.Sc. (mathematics/chemistry/physics) from McGill University.
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Confronting the multicore challenge: parallel computing goes mainstream
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Abstract:
Computing platforms have rapidly moved from single core to multicore designs, giving software developers the opportunity to make the same switch in their designs, from serial to parallel. University programs are beginning to make the corresponding shift, in the underlying principles: from sequential to concurrent. Today’s multicore platform designs are actually straightforward - symmetric, typically with 2 or 4 cores - but the future points to much larger numbers of cores, some of them specialized, with non-uniform memory access, and increasingly sophisticated programming requirements. This talk will explore possible approaches to the challenge, reviewing Intel’s multicore university program history and plans.
Principal Engineer
Corporate Technology Group, Intel
Anwar is a Principal Engineer with Intel’s Microprocessor Technology Lab, working on diverse topics such as parallel language and compiler design, parallel architecture evaluation, optimizing memory system performance, and multimedia applications. Anwar Ghuloum earned degrees at the University of California, Los Angeles (B.S., Computer Science and Engineering) and Carnegie Mellon University’s School of Computer Science (Ph.D., Computer Science, 1996), where his thesis introduced concepts of Nested Data Parallel idioms to traditional automatic parallelizing compilers. Before joining Intel, he co-founded and was the CTO of a fab-less semiconductor startup called Intensys that built programmable, highly parallel image and video processors for the consumer electronics market. Prior to that, Anwar developed novel predictive drug design software for early lead optimization using 3D surface pattern recognition techniques for a biotech startup called MetaXen (acquired by Exelexis Pharmaceuticals). He has also served as a post-doctoral research associate at Stanford University’s Computer Science department. A recurring theme in Anwar’s work has been to bridge high-level application knowledge and low-level parallel architecture constraints with careful parallel language and compiler design to achieve the optimal trade-offs in productivity and performance. Currently, Anwar leads a group of researchers applying this philosophy to Tera-scale software development tools in media, gaming, and high performance computing.
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Presentation Title
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Enabling Future-proof Multi-core Programming for Intel Architectures
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Abstract:
Power consumption is the ultimate limiter to current and future processor design, leading us to focus on more power efficient architectural features such as multiple cores, more powerful vector units, and use of hardware multi-threading (in place of relatively expensive out-of-order techniques). It is (increasingly) well understood that developers face new challenges with multi-core software development. The first of these challenges is a significant productivity burden particular to parallel programming. A big contributor to this burden is the relative difficulty of tracking down data races, which manifest non-deterministically. The second challenge is parallelizing applications so that they effectively scale with new core counts and the inevitable enhancement and evolution of the instruction set. This is a new and subtle qualifier to the benefits of backwards compatibility inherent in Intel® Architecture (IA): performance may not scale forward with new micro-architectures and, in some cases, actually regress. I assert that forward-scaling is an essential requirement for new programming models, tools, and methodologies intended for multi-core software development.
We are implementing a programming model called Ct (C for Throughput Computing) that leverages the strengths of data parallel programming to help address these challenges. Ct is a C++-hosted deterministic parallel programming model integrating the nested data parallelism of Blelloch and bulk synchronous processing of Valiant (with a dash of SISAL for good measure). Ct uses meta-programming and dynamic compilation to essentially embed a pure functional programming language in impure and unsafe C++. A key objective of the Ct project is to create both high-level and low-level abstractions that forward-scale across IA. I will describe the surface API and runtime architecture that we’ve built to achieve this, as well as some performance results
