Become familiar with SSE3 Instructions. SSE3 for the 32-bit Intel® architecture is a set of 13 new instructions that accelerate performance of Streaming SIMD Extensions (SSE) technology, Streaming SIMD Extensions 2 (SSE2) technology, and \87-FP math capabilities. The new technology is compatible with existing software written for Intel architecture microprocessors, and existing software should continue to run correctly, without modification, on microprocessors that incorporate SSE3 instructions.

The 13 new instructions are summarized below. For detailed information on each instruction, see Chapter 3, "Instruction Set Reference," of the Next Generation Intel® Processor: Software Developers Guide.

One instruction improves x87-FP integer conversion: FISTTP.

FISTTP (Store Integer and Pop from x87-FP with Truncation) behaves like the FISTP instruction but uses truncation, irrespective of the rounding mode specified in the floating-point control word (FCW). The instruction converts the top of stack (STO) to integer with rounding to truncate and pop the stack.

FISTTP is available in three precisions: short integer (word or 16-bit), integer (double word or 32-bit), and long integer (64-bit). With FISTTP, applications no longer need to change the FCW when truncation is desired. This instruction is the only x87-FP instruction in the Prescott New Instruction technology.

Three instructions enhance LOAD/MOVE/DUPLICATE performance: MOVSHDUP, MOVSLDUP, and MOVDDUP.

MOVSHDUP loads/moves 128 bits, duplicating the second and fourth 32-bit data elements.

• MOVSHDUP OperandA OperandB
  
  
  • OperandA (128 bits, four data elements): 3_a, 2_a, 1_a, 0_a
  • OperandB (128 bits, four data elements): 3_b, 2_b, 1_b, 0_b
  •  Result (stored in OperandA): 3_b, 3_b, 1_b, 1_b
    
    

MOVSLDUP loads/moves 128-bits, duplicating the first and third 32-bit data elements.

• MOVSLDUP OperandA OperandB
  
  
  • OperandA (128 bits, four data elements): 3_a, 2_a, 1_a, 0_a
  • OperandB (128 bits, four data elements): 3_b, 2_b, 1_b, 0_b
  • Result (stored in OperandA): 2_b, 2_b, 0_b, 0_b
    
    

MOVDDUP loads/moves 64-bits (bits[63-0] if the source is a register) and returns the same 64 bits in both the lower and upper halves of the 128-bit result register. This action duplicates the 64 bits from the source.

• MOVDDUP OperandA OperandB
  
  
  • OperandA (128 bits, two data elements): 1_a, 0_a
  • OperandB (64 bits, one data element): 0_b
  • Result (stored in OperandA): 0_b, 0_b
    
    

One instruction provides specialized 128-bit unaligned data load: LDDQU.

LDDQU is a special 128-bit unaligned load designed to avoid cache-line splits. If the address of the load is aligned on a 16-byte boundary, LDQQU loads the 16 bytes requested. If the address of the load is not aligned on a 16-byte boundary, LDDQU loads a 32-byte block starting at the 16-byte aligned address immediately below the load request. It then extracts the requested 16 bytes. The instruction provides significant performance improvement on 128-bit unaligned memory accesses at the cost of some usage-model restrictions.

Two instructions provide packed addition/subtraction: ADDSUBPS and ADDSUBPD.

ADDSUBPS has two 128-bit operands. The instruction performs single-precision addition on the second and fourth pairs of 32-bit data elements within the operands, and single-precision subtraction on the first and third pairs. This instruction is effective at evaluating complex products on packed single-precision data.

• ADDSUBPS OperandA OperandB
  
  
  • OperandA (128 bits, four data elements): 3_a, 2_a, 1_a, 0_a
  • OperandB (128 bits, four data elements): 3_b, 2_b, 1_b, 0_b
  • Result (stored in OperandA): 3_a+3_b, 2_a-2_b, 1_a+1_b, 0_a-0_b
    
    

ADDSUBPD has two 128-bit operands. The instruction performs double-precision addition on the second pair of quadwords, and double-precision subtraction on the first pair. This instruction is useful when evaluating complex products on packed double-precision data.

• ADDSUBPD OperandA OperandB
  
  
  • OperandA (128 bits, two data elements): 1_a, 0_a
  • OperandB (128 bits, two data elements): 1_b, 0_b
  • Result (stored in OperandA): 1_a+1_b, 0_a-0_b
    
    

Four instructions provide horizontal addition/subtraction: HADDPS, HSUBPS, HADDPD, and HSUBPD.

Most SIMD instructions operate vertically. This means that the result in position i of the result is a function of the elements in position i of both operands. Horizontal addition/subtraction operates horizontally. This means that contiguous data elements from the same operand are used to produce a result data element.

HADDPS performs a single-precision addition on contiguous data elements. The first data element of the result is obtained by adding the first and second elements of the first operand. The second element is obtained by adding the third and fourth elements of the first operand. The third element is obtained by adding the first and second elements of the second operand. The fourth element is obtained by adding the third and fourth elements of the second operand.

• HADDPS OperandA OperandB
  
  
  • OperandA (128 bits, four data elements): 3_a, 2_a, 1_a, 0_a
  • OperandB (128 bits, four data elements): 3_b, 2_b, 1_b, 0_b
  • Result (Stored in OperandA): 3_b+2_b, 1_b+0_b, 3_a+2_a, 1_a+0_a
    
    

HSUBPS performs a single-precision subtraction on contiguous data elements. The first data element of the result is obtained by subtracting the second element of the first operand from the first element of the first operand. The second element is obtained by subtracting the fourth element of the first operand from the third element of the first operand. The third element is obtained by subtracting the second element of the second operand from the first element of the second operand. The fourth element is obtained by subtracting the fourth element of the second operand from the third element of the second operand.

• HSUBPS OperandA OperandB
  
  
  • OperandA (128 bits, four data elements): 3_a, 2_a, 1_a, 0_a
  • OperandB (128 bits, four data elements): 3_b, 2_b, 1_b,0_b
  • Result (Stored in OperandA): 2_b-3_b, 0_b-1_b, 2_a-3_a, 0_a-1_a
    
    

HADDPD performs a double-precision addition on contiguous data elements. The first data element of the result is obtained by adding the first and second elements of the first operand. The second element is obtained by adding the first and second elements of the second operand.

• HADDPD OperandA OperandB
  
  
  • OperandA (128 bits, two data elements): 1_a, 0_a
  • OperandB (128 bits, two data elements): 1_b, 0_b
  • Result (Stored in OperandA): 1_b+0_b, 1_a+0_a
    
    

HSUBPD performs a double-precision subtraction on contiguous data elements. The first data element of the result is obtained by subtracting the second element of the first operand from the first element of the first operand. The second element is obtained by subtracting the second element of the second operand from the first element of the second operand.

• HSUBPD OperandA OperandB
  
  
  • OperandA (128 bits, two data elements): 1_a, 0_a
  • OperandB (128 bits, two data elements): 1_b, 0_b
  • Result (Stored in OperandA): 0_b-1_b, 0_a-1_a
    
    

Two instructions improve synchronization between agents: MONITOR and MWAIT.

1. MONITOR sets up an address range used to monitor write-back stores.
   
   
2. MWAIT enables a logical processor to enter into an optimized state while waiting for a write-back store to the address range set up by the MONITOR instruction.

Support for MONITOR/MWAIT is indicated by the CPUID MONITOR/MWAIT. Software need not check for support of SSE in order to use the MONITOR/MWAIT.